1. Field of the Invention
The present invention generally relates to semiconductor manufacturing. Particularly, the present invention relates to a semiconductor device with an enhanced arrangement of vertical interconnect accesses (vias). More particularly, the present invention relates to a via arrangement with offset and a semiconductor device having the via arrangement.
2. Description of the Related Art
Vias and related applications are well known in the field of semiconductor devices. For example, vias are commonly used to electronically connect different layers in semiconductor wafers. In the semiconductor field, it is usually necessary to implement high-density via connections in limited areas. For instance, high-density via connections may be typically required given that chips on a semiconductor wafer are usually coupled to pads. When it is necessary to connect a chip to other elements located on different layers of the wafer, pads have to be connected to different layers of the wafer. Because pads have limited areas, it is often required to arrange a large amount of vias in limited areas to improve the conductivity performance.
FIG. 1 illustrates a via arrangement in the prior art. In the prior art, vias are regularly arranged with a certain relation to the crystal orientation of the wafer. As illustrated in FIG. 1, the wafer has the [001] orientation, while the vias are arranged in the [110] orientation. For the convenience of description, the above arrangement is illustrated in a coordinate system having a horizontal axis x and a vertical axis y. It should be understood that the center of any via (or any point on a via) can be used as the origin of the coordinate system.
Vias in FIG. 1 are arranged in a matrix having rows parallel to or aligned with the x axis and having columns parallel to or aligned with the y axis. As illustrated in FIG. 1, there is a first spacing d1 between two adjacent rows, and there is a second spacing d2 between two adjacent columns. The first spacing may be different from the second spacing.
For illustration, three columns of vias A, B, and C are illustrated in FIG. 1, wherein vias in each column are numbered with 1, 2, and 3 for distinguishing the vias from each other. Vias having the same number (e.g., A1, B1, and C1) are considered as corresponding vias in different columns and are in a same row of the matrix. Vias having the same alphabetic character (e.g., A1, A2, and A3) are considered as corresponding vias in different rows and are in a same column of the matrix. Although a 3×3 via array is illustrated in FIG. 1, the 3×3 via array is merely an example for illustration, and those skilled in the art may employ arrays having other numbers of vias.
In some applications, it may be desired to arrange vias with a process that allows a minimal distance d, so that as many vias as possible can be arranged in a limited area. For example, a minimal distance d may exist between the via A2 and each of the vias A1, A3, B2, and C2, and d1=d2=d. FIG. 2 illustrates a schematic cross-sectional view of a structure of a via. In FIG. 2, a via in a silicon wafer 200 comprises a dielectric layer 201, a barrier/glue layer 202, and a filled metal 203. A problem of existing vias is that various materials, such as dielectrics, metals, etc., have to be filled in wafers in order to manufacture vias. Due to the different material characteristics between filled materials and the wafer material (such as Si), accumulated stress exists in the wafer 200. The stress is increasingly accumulated and may cause a crack x as shown in the proximity of the via A3 in FIG. 1. The crack x may cause device failure, such as short circuit, break, etc. The presence of the crack x must be considered in the design of the device, which may limit minimal spacing between various vias, leading to a restricted number of vias arranged in a limited area. Alternatively, a larger area is needed to arrange the vias to reserve a sufficient margin for possible cracks; the arrangement with an increased area may lower conductivity performance and/or may increase cost.